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参数资料
| 型号： | MC68HC05RC8DW |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 95/122页 |
| 文件大小： | 445K |
| 代理商： | MC68HC05RC8DW |
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Carrier Modulator Transmitter (CMT)
General Release Specification
MC68HC05RC16 — Rev. 3.0
74
Carrier Modulator Transmitter (CMT)
MOTOROLA
of the modulator. The secondary carrier high and low time values are
undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
IROLN and IROLP — IRO Latch Control
Reading IROLN or IROLP reads the state of the IRO latch. Writing
IROLN updates the IRO latch with the data being written on the
negative edge of the internal processor clock (fosc/2). Writing IROLP
updates the IRO latch on the positive edge of the internal processor
clock; for example, one fosc period later. The IRO latch is clear out of
reset.
NOTE:
Writing to CHR1 to update IROLN or to CLR1 to update IROLP will also
update the primary carrier high and low data values. Care should be
taken that bits 5–0 of the data to be written to CHR1 or CHL1 should
contain the desired values for the primary carrier high or low data.
9.5 Modulator
The modulator consists of a 12-bit down counter with underflow
detection which is loaded from the modulation mark period from the
mark buffer register, MBUFF. When this counter underflows, the
modulator gate is closed and a 12-bit comparator is enabled which
continually compares the logical complement of the contents of the (still)
decrementing counter with the contents of the modulation space period
register, SREG. When a match is obtained, the modulator control gate
is opened again. Should SREG = 0, the match will be immediate and no
space period will be generated (for instance, for FSK protocols which
require successive bursts of different frequencies). When the match
occurs, the counter is reloaded with the contents of MBUFF, SREG is
reloaded with the contents of its buffer, SBUFF, and the cycle repeats.
The MCGEN bit in the MCSR must be set to enable the modulator timer.
The 12-bit MBUFF and SBUFF registers are accessed through three
8-bit modulator period registers, MDR1, MDR2, and MDR3.
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