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参数资料
| 型号： | MC68HC05RC8FN |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 100/122页 |
| 文件大小： | 2962K |
| 代理商： | MC68HC05RC8FN |
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Carrier Modulator Transmitter (CMT)
Modulator
MC68HC05RC16 — Rev. 3.0
General Release Specification
Carrier Modulator Transmitter (CMT)
Where fcg is the frequency output from the carrier generator. For an
example of extended space operation, see Figure 9-9.
NOTE:
The EXSPC feature can be used to emulate a zero mark event.
Figure 9-9. Extended Space Operation
9.5.3.1 End Of Cycle (EOC) Interrupt
At the end of each cycle (when the counter is reloaded from MBUFF),
the end of cycle (EOC) flag is set. If the interrupt enable bit was
previously set, an interrupt also will be issued to the CPU. The EOC
interrupt provides a means for the user to reload new mark/space values
into the MBUFF and SBUFF registers. As the EOC interrupt is coincident
with reloading the counter, MBUFF does not require additional buffering
and may be updated with a new value for the next period from within the
EOC interrupt service routine (ISR). To allow both mark and space
period values to be updated from within the same ISR, SREG is buffered
by SBUFF. The contents written to SBUFF are transferred to the active
register SREG at the end of every cycle regardless of the state of the
EOC flag. The EOC flag is cleared by a read of the modulator control and
status register (MCSR) followed by an access of MDR2 or MDR3. The
EOC flag must be cleared within the ISR to prevent another interrupt
being generated after exiting the ISR. If the EOC interrupt is not being
used (IE = 0), the EOC flag need not be cleared.
SET EXSPC
CLEAR EXSPC
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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