MC68HC05SR3 PDF资料下载(69/96 页)High-density Complementary Metal Oxide Semiconductor (HCMOS)

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参数资料

型号：	MC68HC05SR3
厂商：	飞思卡尔半导体(中国)有限公司
英文描述：	High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units
中文描述：	高密度互补金属氧化物半导体（HCMOS）微控制器单元
文件页数：	69/96页
文件大小：	3045K
代理商：	MC68HC05SR3

MC68HC05SR3

Freescale

9-3

LOW POWER MODES

9.3

SLOW Mode

The SLOW mode function is controlled by the SM bit in the Miscellaneous Control Register. When

the SM bit is set, the internal bus clock is divided by 16, resulting to a frequency equal to the

oscillator frequency divide by 32. This feature permits a slow down of all the internal operations

and thus reduces power consumption — particularly useful while in WAIT mode. The SM bit is

automatically cleared while going to STOP mode.

SM — Slow Mode

1 (set)

–

Slow mode enabled. Internal bus frequency fOP=fOSC ÷ 32.

0 (clear) –

Slow mode disabled. Internal bus frequency fOP=fOSC ÷ 2.

9.4

Data-Retention Mode

If the Low Voltage Reset function is not enabled, the contents of RAM and CPU registers are

retained at supply voltages as low as 2Vdc. This is called the data-retention mode where the data

is held, but the device is not guaranteed to operate. The RESET pin must be held low during

data-retention mode.

The Low Voltage Reset Function is enabled/disabled by the LVRE bit in the Miscellaneous Control

LVRE — Low Voltage Reset Enable

1 (set)

–

Low Voltage Reset function enabled.

0 (clear) –

Low Voltage Reset function disabled.

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

Miscellaneous Control Register

$0C

KBIE

KBIC

INTO

INTE LVRE

IRQ2F IRQ2E 0001 0000