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参数资料
| 型号： | MC68HC05V12CFNR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 68/135页 |
| 文件大小： | 2080K |
| 代理商： | MC68HC05V12CFNR2 |
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General Description
Functional Pin Descriptions
MC68HC05V12 — Rev. 2.0
Technical Data
MOTOROLA
General Description
31
NON-DISCLOSURE
AGREEMENT
REQUIRED
1.6.7 IRQ (Maskable Interrupt Request)
This input pin drives the asynchronous IRQ interrupt function of the
CPU. The IRQ interrupt function has a programmable mask option to
select either negative edge-sensitive triggering or both negative edge-
sensitive and low level-sensitive triggering. The IRQ input requires an
external resistor to V
DD for wire-OR operation, if desired. If the IRQ pin
is not used, it must be tied to the VDD supply. The IRQ pin contains an
internal Schmitt trigger as part of its input to improve noise immunity.
Each of the PC0–PC7 I/O pins may be connected as an OR function with
the IRQ interrupt function. This capability allows keyboard scan
applications where the transitions on the I/O pins will behave the same
as the IRQ pin. The edge or level sensitivity selected by a mask option
for the IRQ pin does not apply to the port C input/output (I/O) pin
interrupt. The I/O pin interrupt is always negative edge-sensitive. See
Section 4. Interrupts for more details on the interrupts.
1.6.8 PA0–PA6
These seven I/O lines comprise port A. The state of any pin is software
programmable, and all port A lines are configured as inputs during
power-on or reset. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
1.6.9 PB0–PB3 (SPI Pins), PB4/PWMA, PB5/PWMB, PB6/TCMP, and PB7/TCAP
These eight I/O lines comprise port B. The state of any pin is software
programmable, and all port B lines are configured as inputs during
power-on or reset. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
PB0–PB3 are shared with serial peripheral interface (SPI) functions. See
Section 10. Serial Peripheral Interface (SPI) for more details
concerning the operation of the SPI and configuration of these pins.
PB6 and PB7 are also shared with timer functions. The TCAP pin
controls the input capture feature for the on-chip 16-bit timer. The TCMP
pin provides an output for the output compare feature of the on-chip
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