
Functional Description
MC68HC908GP32 MC68HC08GP32 Data Sheet, Rev. 7
Freescale Semiconductor
133
The second condition states that as long as VTST is maintained on the IRQ pin after entering monitor
mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied
to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST
can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor
mode.
Figure 15-2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just
1 x VDD voltage is applied to the IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate
of 9600, as the internal bus frequency is automatically set to the external frequency divided by four.
Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart
Enter monitor mode with pin configuration shown in
Figure 15-1 by pulling RST low and then high. The
rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See
15.4 Security.) After the
security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.
NOTE
The PTA7 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high to enter monitor mode properly.
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST low will not exit
monitor mode in this situation.
IS VECTOR
BLANK?
POR
TRIGGERED?
NORMAL USER
MODE
MONITOR MODE
EXECUTE
MONITOR
CODE
NO
YES
POR RESET