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| 型号： | MC68HC705JB4P |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 45/134页 |
| 文件大小： | 1237K |
| 代理商： | MC68HC705JB4P |
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GENERAL RELEASE SPECIFICATION
February 24, 1999
MOTOROLA
GENERAL DESCRIPTION
MC68HC05JB4
1-6
REV 2
1.4.3 RESET
This is an I/O pin. This pin can be used as an input to reset the MCU to a known
start-up state by pulling it to the low state. The RESET pin contains a steering
diode to discharge any voltage on the pin to VDD, when the power is removed. An
internal pull-up is also connected between this pin and VDD. The RESET pin con-
tains an internal Schmitt trigger to improve its noise immunity as an input. This pin
is an output pin if LVR triggers an internal reset.
1.4.4 IRQ (MASKABLE INTERRUPT REQUEST)
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ
interrupt function has a mask option to provide either only negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering. If the
option is selected to include level-sensitive triggering, the IRQ input requires an
external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains
an internal Schmitt trigger as part of its input to improve noise immunity.
NOTE
Each of the PA0 thru PA3 I/O pins may be connected as an OR function with the
IRQ interrupt function by a mask option. This capability allows keyboard scan
applications where the transitions or levels on the I/O pins will behave the same
as the IRQ pin. The edge or level sensitivity selected by a separate mask option
for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal.
1.4.5 V3.3
This is an output reference voltage nominally set at 3.3 volt DC.
1.4.6 D+ and D–
These two lines carry the USB differential data. For low speed device such as
MC68HC05JB4, a 1.5 k
resistor is required to be connected across D– and 3.3V
for proper signal termination.
1.4.7 PA0-PA7
These eight I/O lines comprise Port-A. PA0 to PA7 are push-pull pins with internal
pull-up resistors. The state of any pin is software programmable and all Port A
lines are congured as inputs during power-on or reset. The internal pull-up resis-
tor on PA0-4 is software enable. The PA0 thru PA3 can be connected via an inter-
nal NAND gate to the IRQ interrupt function enabled by a mask option. PA5 thru
PA7 has built in 10mA pull-down device for direct LED drive. In addition, PA6 and
PA7 both have Slow Falling Edge Control which is enabled by software and can
sink 25mA current selectable by mask option. PA0 thru PA4 have built-in schmitt
triggered input. PA4 can be used as an extra interrupt pin (IRQ2) when IRQ2 inter-
rupt is enabled.
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