参数资料
型号: MC68HC705P6AMDW
厂商: Freescale Semiconductor
文件页数: 51/98页
文件大小: 0K
描述: IC MCU 4.6K OTP 2.1MHZ 28-SOIC
标准包装: 26
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 4.5KB(4.5K x 8)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
A/D Conversion Data Register (ADC)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
55
ADRC — RC Oscillator Control
When ADRC is set, the A/D subsystem operates from the internal RC oscillator instead of the internal
clock. The RC oscillator requires a time, tRCON, to stabilize before accurate conversion results can be
obtained. See 9.2.2 Reference Voltage (VREFH) for more information.
ADON — A/D Subsystem On
When the A/D subsystem is turned on (ADON = 1), it requires a time, tADON, to stabilize before
accurate conversion results can be attained.
CH2–CH0 — Channel Select Bits
CH2, CH1, and CH0 form a 3-bit field which is used to select an input to the A/D converter. Channels
0–3 correspond to port C input pins PC6–PC3. Channels 4–6 are used for reference measurements.
Channel 7 is reserved. If a conversion is attempted with channel 7 selected, the result will be $00.
Table 9-1 lists the inputs selected by bits CH0-CH3.
If the ADON bit is set and an input from channels 0–4 is selected, the corresponding port C pin’s DDR
bit will be cleared (making that port C pin an input). If the port C data register is read while the A/D is
on and one of the shared input channels is selected using bit CH0–CH2, the corresponding port C pin
will read as a logic 0. The remaining port C pins will read normally. To digitally read a port C pin, the
A/D subsystem must be disabled (ADON = 0), or input channels 5–7 must be selected.
9.6 A/D Conversion Data Register (ADC)
This register contains the output of the A/D converter. See Figure 9-2.
Table 9-1. A/D Multiplexer Input Channel Assignments
Channel
Signal
0
AD0 — port C, bit 6
1
AD1 — port C, bit 5
2
AD2 — port C, bit 4
3
AD3 — port C, bit 3
4
VREFH — port C, bit 7
5
(VREFH + VSS)/2
6
VSS
7
Reserved for factory test
Address: $001D
Bit 7
654321
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 9-2. A/D Conversion Value Data Register (ADC)
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