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参数资料
型号： MC68HC705P9CS
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
封装： CERDIP-28
文件页数： 127/160页
文件大小： 2208K
代理商： MC68HC705P9CS
Resets and Interrupts
Interrupts
MC68HC705P9 — Rev. 4.0
Technical Data
MOTOROLA
Resets and Interrupts
69
5.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
5.4.2 External Interrupt
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/VPP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request. Figure 5-4 shows the IRQ/VPP pin interrupt logic.
Figure 5-4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ/VPP pin is a programmable
option. The IRQ/VPP pin can be negative-edge triggered or negative-
edge- and low-level triggered. The level-sensitive triggering option
allows multiple external interrupt sources to be wire-ORed to the
DQ
CK
CLR
LEVEL-SENSITIVE TRIGGER
(MOR OPTION)
VDD
EXTERNAL
INTERRUPT
REQUEST
RESET
VECTOR FETCH
IRQ/VPP
I
(FROM CCR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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