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参数资料
| 型号： | MC68HC711EA9MFN3 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| 封装： | PLASTIC, LCC-52 |
| 文件页数： | 35/58页 |
| 文件大小： | 583K |
| 代理商： | MC68HC711EA9MFN3 |
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MOTOROLA
MC68HC11EA9
40
MC68HC11EA9TS/D
TOF — Timer Overflow Interrupt Flag
If the TOI enable bit is set when the timer counter register (TCNT) changes from $FFFF to $0000, this
flag is set and an interrupt is generated.
0 = TCNT has not rolled over since either the TOF flag bit was last cleared or the TOI enable bit
was set.
1 = TCNT has rolled over to $0000
RTIF — Real-Time Interrupt Flag
If RTII enable bit is set, this flag is set and an interrupt is generated periodically at the rate determined
by the real-time interrupt rate (RTR[1:0]) bits in PACTL.
0 = No periodic interrupt has occurred since either the RTIF flag bit was last cleared or when the
RTII enable bit was set
1 = A periodic interrupt has occurred
PAOVF — Pulse Accumulator Overflow Interrupt Flag
If the PAOVI enable bit is set when the pulse accumulator counter register (PCNT) rolls over to $0000,
this flag is set and an interrupt is generated.
0 = PCNT has not rolled over since either the PAOVF flag bit was last cleared or the PAOVI enable
bit was set.
1 = PCNT has rolled over to $0000
PAIF — Pulse Accumulator Input Edge Interrupt Flag
If the PAII enable bit is set when an edge is detected on the pulse accumulator input pin (PA7/PAI), this
flag is set and an interrupt is generated.
0 = No edge has been detected on the PAI pin
1 = An edge (rising or falling, depending on configuration) has been detected on the PAI pin
Bits [3:0] — Not Implemented
Always read zero
Bits [7:4] can be written at any time. PR[1:0] can only be written once in the first 64 cycles after reset in
normal modes (SMOD = 0). In special modes (SMOD = 1) PR[1:0] can be written any time.
Bit 7 — Not Implemented
Always reads zero
PAEN — Pulse Accumulator Enable
Refer to 7.4 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode Select
Refer to 7.4 Pulse Accumulator.
PEDGE — Pulse Accumulator Input Edge Select
Refer to 7.4 Pulse Accumulator.
TFLG2 — Timer Interrupt Flag 2
$1025
BIT 7
654321
BIT 0
TOF
RTIF
PAOVF
PAIF
————
RESET:
00000000
PACTL — Pulse Accumulator Control
$1026
BIT 7
654321
BIT 0
—
PAEN
PAMOD
PEDGE
—
I4/O5
RTR1
RTR0
RESET:
00000000
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For More Information On This Product,
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