参数资料
型号: MC68HC805K3DW
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, EEPROM, 2 MHz, MICROCONTROLLER, PDSO16
封装: SOIC-16
文件页数: 72/119页
文件大小: 496K
代理商: MC68HC805K3DW
General Release Specication
Low-Power Modes
MC68HC805K3 — Rev. 1.0
56
Operational Modes
MOTOROLA
6.3.2 Halt Mode
Execution of the STOP instruction with a mask option register bit to
disable the stop mode places the MCU in a low-power halt mode, which
consumes more power than stop mode. In halt mode, the internal
processor clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be
generated from the timer or a reset to be generated from the COP
watchdog timer. Execution of the STOP instruction in the halt mode
automatically clears the I bit in the condition code register and sets the
IRQE enable bit in the IRQ status/control register so that the IRQ
external interrupt is enabled. All other registers, memory, and
input/output lines remain in their previous states.
If timer interrupts are enabled, a timer interrupt causes the processor to
exit halt mode and resume normal operation. Halt mode also can be
exited when an external IRQ or external RESET occurs. When exiting
halt mode, the internal processor clock resumes after a variable delay.
Depending on the mask option register bit state, the maximum oscillator
stabilization delay is 16 or 4064 cycles of the internal processor clock.
Using the mask option register bit to disable the STOP instruction
prevents the STOP instruction from halting the oscillator or affecting the
COP watchdog timer similar to wait mode. However, the recovery
method introduces some startup delay in the processor clock.
NOTE:
Halt mode is not intended for normal use, but is provided to keep the
COP watchdog timer active if the STOP instruction opcode is executed
inadvertently.
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