Timer Interface Module (TIM)
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
138
Timer Interface Module (TIM)
MOTOROLA
14.7 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear status bits during the break state. See
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE
bit. If a status bit is cleared during the break state, it remains cleared when the MCU
exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), software can read and write I/O registers during the break
state without affecting status bits. Some status bits have a two-step read/write
clearing procedure. If software does the first step on such a bit before the break,
the bit cannot change during the break state as long as BCFE is at 0. After the
break, doing the second step clears the status bit.
14.8 Input/Output Signals
Port A shares three of its pins with the TIM. Two TIM channel I/O pins are
PTA0/TCH0 and PTA1/TCH1 and an alternate clock source is PTA2/TCLK.
14.8.1 TIM Clock Pin (PTA2/TCLK)
PTA2/TCLK
is an external clock input that can be the clock source for the TIM
counter instead of the prescaled internal bus clock. Select the PTA2/TCLK input
input regardless of port pin initialization.
14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1)
Each channel I/O pin is programmable independently as an input capture pin or an
output compare pin. PTA0/TCH0 can be configured as a buffered output compare
or buffered PWM pin.
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Freescale Semiconductor, Inc.
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