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参数资料
| 型号： | MC68LC060ZU75 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 6/10页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 68K 75MHZ 304-TBGA |
| 标准包装： | 27 |
| 系列： | M680x0 |
| 处理器类型： | M680x0 32-位 |
| 速度： | 75MHz |
| 电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 304-LBGA |
| 供应商设备封装： | 304-TBGA（31x31） |
| 包装： | 托盘 |
MOTOROLA
MC68060 PRODUCT INFORMATION
5
EXECUTION UNIT
The MC68060 execution unit carries out logical and arithmetic operations. The execution unit contains an
instruction fetch unit, an integer unit, a branch cacheand a floating-point unit. The superscalar design of the
MC68060 provides dual execution pipelines in the instruction integer unit, providing simultaneous instruction
execution.
The superscalar operation of the execution unit can be disabled in software, turning off the second execution
pipeline for debugging. Disabling the superscalar operation also lowers power consumption.
INSTRUCTION FETCH UNIT
The instruction fetch unit contains an instruction fetch pipeline and the logic that interfaces to the branch cache.
The instruction fetch pipeline consists of four stages, providing the ability to prefetch instructions in advance
of their actual use in the instruction execution controller. The continuous fetching of instructions keeps the in-
struction execution unit busy for the greatest possible performance. Every instruction passes through each of
the four stages before entering the integer unit. The four stages in the instruction fetch pipeline are:
1) Instruction Address Calculation—The virtual address of the instruction is determined.
2) Instruction Fetch—The instruction is fetched from memory.
3) Early Decode—The instruction is pre-decoded into a fixed length format for pipeline control information.
4) Instruction Buffer—The instruction and its pipeline control information are buffered until the
integer execution pipeline is ready to process the instruction.
BRANCH CACHE
The branch cache plays a major role in achieving the performance levels of the MC68060. The concept of the
branch cache is to provide a mechanism that allows the instruction fetch pipeline to detect and change the
instruction stream before the change of flow affects the integer unit.
The branch cache is examined for a valid branch entry after each instruction fetch address is generated in the
instruction fetch pipeline. If a hit does not occur in the branch cache, the instruction fetch pipeline continues to
fetch instructions sequentially. If a hit occurs in the branch cache, indicating a branch taken instruction, the
current instruction stream is discarded and a new instruction stream is fetched starting at the location indicated
by the branch cache.
INTEGER UNIT
The integer unit contains dual integer execution pipelines, interface logic to the FPU (MC68060 only), and
control logic for data written to the data cache and MMU. The superscalar design of the dual integer execution
pipelines provides for simultaneous instruction execution, which allows processing more than one instruction
during each machine clock cycle. The net effect of this is a software-invisible pipeline capable of sustained
execution rates of less than one machine clock cycle per instruction for the M68000 instruction set.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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