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| 型号： | MC68LC302PU25CT |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件页数： | 87/128页 |
| 文件大小： | 641K |
| 代理商： | MC68LC302PU25CT |
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ETHERNET Controller
4-22
MC68EN302 REFERENCE MANUAL
MOTOROLA
Receive Frame Status
— Generates the M, LG, NO, SH, CR, OV and CL status fields which are written into
the end of frame receive buffer descriptor to provide status on the reception of the
frame. The definition of these fields is based on the Layer Management section of
the 802.3 standard.
The serial interface consists of TCLK, TENA, TX, RCLK, RENA, RX and CLSN. The polarity
of the TENA, TX, RENA, RX and CLSN signals is positive (1 or asserted = Voh or Vih). Zero
or more RCLK cycles are required following the deassertion of RENA at the end of a receive
frame. Logic in this module will detect end of receive frame condition and switch in TCLK if
necessary to complete flushing the frame through the receive data path and into the receive
FIFO.
4.5.3 ETHERNET LOOPBACK
The transmit to receive loopback function is selected by the LOOP bit in the ECNFIG
register. While in the internal loopback mode, TENA will not assert. Any assertion of RENA
and CLSN will be ignored.
4.6 ETHERNET AR (ADDRESS RECOGNITION)
The MC68EN302 supports 64-entry internal address recognition with 48 bit address
matching for receive address filtering. Address Recognition memory is written as a normal
memory cycle. Note that unused entries in the AR memory map do not return DTACK if
accessed.
There are two modes for address recognition: perfect entries, and hash mode. The mode
selected determines the way in which memory is partitioned. When perfect-entry mode is
selected, the entire memory is devoted to storing addresses for 64 perfect matches. When
hash mode is selected, 8 bytes are used to store a logical address filter, and 372 bytes are
used to store addresses for 62 perfect matches.
In hash mode, a logical address filter mask is used which requires the processor to perform
final filtering. As the incoming data stream goes through the CRC Generator, once the 48th
bit of the destination address has passed this circuitry, the six most significant bits of the
CRC are sampled. Those 6 bits become an address which selects one of the 64 bits in the
logical address filter mask. If the mask bit selected is a “1”, the address matches and the
packet is accepted. When programming the hash table, the task of mapping a destination
address to one of 64 bit positions requires a computer program to generate the CRC codes
for the addresses desired. The 6 most significant bits of a given addresses’ CRC becomes
the pointer into that addresses’ hash table entry. For Ethernet, the CRC polynomial is
CRC32 or:
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
There is no rule on what type of address can be used in which type of address matching
mode. Either physical or multicast addresses may be stored as either a perfect match or
hash table entries. If an address matches both a perfect entry and a hash entry, the perfect
entry takes precedence.
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