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| 型号： | MC68MH360ZQ33LR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 134/158页 |
| 文件大小： | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 标准包装： | 180 |
| 系列： | M683xx |
| 处理器类型： | M683xx 32-位 |
| 速度： | 33MHz |
| 电压： | 5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 357-BBGA |
| 供应商设备封装： | 357-PBGA（25x25） |
| 包装： | 带卷 (TR) |
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Chapter 5. Buffer Descriptors
5.3 Placement of Buffer Descriptors
The internal dual-ported RAM is used to store the buffer descriptors for all non-QMC
operation. This solution causes minimum loading of the external bus. When starting any
operation or switching between buffers during operations, several accesses must be made
by the CPM to nd the actual data buffers and to read and write control and status
information. This process is unseen by the user for internal accesses, and any external bus
master or memory refresh control can occur uninterrupted.
5.3.1 MC68MH360 Internal Memory Structure
To support 32 channels on the MC68MH360, the entire 2-Kbyte dual-ported RAM is
needed for channel-specic parameters. Each logical channel occupies 64 bytes; thus 32
channels require 2 Kbytes. No conicts arise for QMC operation since it uses external
memory for the buffer descriptors; however, buffer descriptors for other protocols must be
in internal memory.
If the QMC uses all 32 channels, no space is left in the lower 2-Kbyte area; the only free
areas are in the RAM pages, each 192-bytes large. Depending on the functions, channels
and protocols used, some areas remain free for buffer descriptors. If a function is not
enabled, its parameter RAM area may be used.
If fewer than 32 logical channels are used or if physical channels are concatenated to super
channels, space is freed in the dual-ported RAM. Each logical channel creates a 64-byte
hole in the dual-ported RAM that an SCC can use for buffer descriptors. QMC channels can
use this area rather than external memory for buffer descriptors, reducing the load on the
external bus.
If the external 64-Kbyte area overlaps the internal dual-ported RAM, external and internal
buffer descriptors can be combined for the QMC. This is controlled by the show cycles
setting. If split buses are used with SHEN1/SHEN0 = 00, a memory access is always made
to the dual-ported RAM if the source is an internal master. For more information, refer to
the description of the module conguration register in the MC68360 Quad Integrated
Communications Controller User’s Manual.
Figure 5-5 shows the internal memory map. Figure 5-6 shows the SCC parameter RAM
overlap example. Figure 5-7 through Figure 5-10 give a detailed memory map for each
SCC, showing parameter RAM usage for different functions.
RAM page one is dedicated to SCC1 and for miscellaneous storage.
RAM page two is dedicated for SCC2, RISC timers, and the SPI channel.
RAM page three is dedicated for SCC3, SMC1, and IDMA1 operations.
RAM page four is dedicated for SCC4, SMC2, and IDMA2 operations.
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For More Information On This Product,
Go to: www.freescale.com
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