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参数资料
| 型号： | MC68SEC000FU20R2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 20 MHz, MICROPROCESSOR, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件页数： | 4/8页 |
| 文件大小： | 42K |
| 代理商： | MC68SEC000FU20R2 |
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MC68SEC000 PRODUCT INFORMATION
MOTOROLA
Figure 2. Functional Signal Groups
Address Bus (A23-A0)
This 24-bit, unidirectional, three-state bus can address 16 Mbytes of data. It provides the address for bus
operation during all cycles except interrupt cycles. During interrupt cycles, A3, A2, and A1 reflect the level
of the interrupt being serviced, while A23-A4 and A0 are set to a logic high.
Data Bus (D15-D0)
This 16-bit, bidirectional, three-state bus is the general-purpose data path. Using the mode pin, you can
statically select either 8- or 16-bit modes for data transfer.
Asynchronous Bus Control
Asynchronous data transfers are handled using the following control signals: address strobe (AS), read/
write (R/W), upper and lower data strobes (UDS, LDS), and data transfer acknowledge (DTACK). The
address strobe signal indicates there is a valid address on the address bus. Read/write defines the data bus
transfer as a read or write cycle. The data strobes control the flow of data on the data bus and the data
transfer acknowledge indicates that the data transfer is complete.
Bus Arbitration Control
In multiple bus master systems, the bus arbitration circuit determines which device will be the bus master.
The bus request (BR) indicates that an external device requires bus mastership. A bus grant (BG) indicates
to all other potential bus master devices that the controller will release bus control at the end of the current
bus cycle.
ADDRESS BUS
DATA BUS
ASYNCHRONOUS
BUS CONTROL
BUS ARBITRATION
CONTROL
INTERRUPT
CONTROL
PROCESSOR
STATUS
A23-A0
D15-D0
AS
R/W
UDS
LDS
DTACK
BERR
RESET
HALT
MODE
SYSTEM
CONTROL
VCC
GND
CLK
MC68SEC000
FC0
FC1
FC2
IPL0
IPL1
IPL2
AVEC
BR
BG
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