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参数资料
| 型号： | MC74AC161DWR2 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 计数器 |
| 英文描述： | AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封装： | PLASTIC, SOIC-16 |
| 文件页数： | 9/16页 |
| 文件大小： | 121K |
| 代理商： | MC74AC161DWR2 |
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
http://onsemi.com
2
Figure 2. Logic Symbol
*MR for
′161
*SR for
′163
PE P0 P1 P2
CEP
P3
CET
CP
*R Q0 Q1 Q2 Q3
TC
FUNCTIONAL DESCRIPTION
The MC74AC161/ACT161
and MC74AC163/ACT163
count modulo–16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip–flops are driven in parallel through a clock buffer.
Thus all changes of the Q outputs (except due to Master
Reset of the
′161) occur as a result of, and synchronous
with, the LOW–to–HIGH transition of the CP input signal.
The circuits have four fundamental modes of operation, in
order
of
precedence:
asynchronous
reset
(
′161),
synchronous reset (
′163), parallel load, count–up and hold.
Five
control
inputs
–
Master
Reset
(MR,
′161),
Synchronous Reset (SR,
′163), Parallel Enable (PE), Count
Enable Parallel (CEP) and Count Enable Trickle (CET) –
determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW. A
LOW signal on SR overrides counting and parallel loading
and allows all outputs to go LOW on the next rising edge
of CP. A LOW signal on PE overrides counting and allows
information on the Parallel Data (Pn) inputs to be loaded
into the flip–flops on the next rising edge of CP. With PE
and MR (
′161) or SR (′163) HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The MC74AC161/ACT161 and MC74AC163/ACT163
use D–type edge–triggered flip–flops and changing the SR,
PE, CEP and CET inputs when the CP is in either state does
not cause errors, provided that the recommended setup and
hold times, with respect to the rising edge of CP, are
observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement
synchronous multistage counters, the TC outputs can be
used with the CEP and CET inputs in two different ways.
Please refer to the MC74AC568 data sheet. The TC output
is subject to decoding spikes due to internal race conditions
and is therefore not recommended for use as a clock or
asynchronous reset for flip–flops, counters or registers.
Logic Equations:
Count Enable = CEPCETPE
TC = Q0Q1Q2Q3CET
MODE SELECT TABLE
*SR
PE
CET
CEP
Action on the Rising
Clock Edge ( )
L
X
Reset (Clear)
H
L
X
Load (Pn → Qn)
H
Count (Increment)
H
L
X
No Change (Hold)
H
X
L
No Change (Hold)
*For
′163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Figure 3. State Diagram
15
0
14
13
12
5
4
6
7
8
1
2
3
11
10
9
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