参数资料
型号: MC74AC373DW
厂商: ON Semiconductor
文件页数: 5/12页
文件大小: 0K
描述: IC LATCH OCT TRANSP 3ST 20-SOIC
产品变化通告: LTB Notification 03/Jan/2008
标准包装: 38
系列: 74AC
逻辑类型: D 型透明锁存器
电路: 8:8
输出类型: 三态
电源电压: 2 V ~ 6 V
独立电路: 1
延迟时间 - 传输: 7ns
输出电流高,低: 24mA,24mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC
包装: 管件
MC74AC373, MC74ACT373
http://onsemi.com
2
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
H
X
Z
L
H
L
H
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O0 = Previous O0 before LOW-to-HIGH Transition of Clock
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight Dtype
latches with 3state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGHtoLOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
Figure 3. Logic Diagram
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D1
D2
D3
D4
D5
D6
D7
LE
OE
D0
NOTE:
This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
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