参数资料
型号: MC74HC11AD
厂商: MOTOROLA INC
元件分类: 通用总线功能
英文描述: Triple 3-Input AND Gate
中文描述: HC/UH SERIES, TRIPLE 3-INPUT AND GATE, PDSO14
封装: PLASTIC, SOIC-14
文件页数: 3/6页
文件大小: 211K
代理商: MC74HC11AD
MC74HC112
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Figures 1 and 4)
4.5
30
20
6.0
21
24
32
tPLH,
Maximum Propagation Delay, Reset to Q or Q
2.0
155
195
26
235
ns
tPHL
(Figures 2 and 4)
4.5
33
50
6.0
13
41
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
35
pF
(Figure 3)
4.5
20
30
(Figure 3)
4.5
6.0
3
3
25
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
2.0
6.0
100
17
125
3
3
150
26
3
3
ns
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
80
16
100
21
120
24
ns
(Figure 2)
4.5
6.0
16
14
20
24
20
tr, tf
Maximum Input Rise and Fall Times
2.0
6.0
1000
400
1000
400
20
17
1000
400
ns
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
相关PDF资料
PDF描述
MC74HC11ADT Triple 3-Input AND Gate
MC74HC11AN Triple 3-Input AND Gate
MC74HC11D Triple 3-Input AND Gate
MC74HC11N Triple 3-Input AND Gate
MC74HC139AD Dual 1-of-4 Decoder/Demultiplexer
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