参数资料
型号: MC74HC4060ADTR2
厂商: ON SEMICONDUCTOR
元件分类: 通用总线功能
英文描述: 14-Stage Binary Ripple Counter With Oscillator
中文描述: HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16
封装: LEAD FREE, TSSOP-16
文件页数: 5/11页
文件大小: 256K
代理商: MC74HC4060ADTR2
MC54/74HC4060A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative–edge triggering clock input. A high–to–low tran-
sition on this input advances the state of the counter. Osc In
may be driven by an external clock source.
Reset (Pin 12)
Active–high reset. A high level applied to this input asynch-
ronously resets the counter to its zero state (forcing all Q out-
puts low) and disables the oscillator.
OUTPUTS
Q4—Q10, Q12–Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active–high outputs. Each Qn output divides the Clock
input frequency by 2N. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator
(See NO TAG and NO TAG). When Osc In is being driven
with an external clock source, Osc Out 1 and Osc Out 2 must
be left open circuited. With the crystal oscillator configuration
in Figure 6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
tw
tf
Osc In
Q
VCC
GND
90%
50%
10%
tr
tw
90%
50%
10%
tPHL
1/fMAX
tPLH
tTLH
tTHL
Reset
VCC
GND
tPHL
50%
Figure 1.
Figure 2.
Q
VCC
GND
50%
Osc In
50%
trec
50%
Qn
VCC
GND
50%
Qn+1
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
Figure 4. Test Circuit
tPLH
tPHL
相关PDF资料
PDF描述
MC74HC4060ADT 14-Stage Binary Ripple Counter With Oscillator
MC74HC4060AN 14-Stage Binary Ripple Counter With Oscillator
MC74HC4060DT 14-Stage Binary Ripple Counter with Oscillator
MC74HC4060N 14-Stage Binary Ripple Counter with Oscillator
MC74HC4511 BCD-to-Seven-Segment Latch/Decoder/Display Driver
相关代理商/技术参数
参数描述
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