参数资料
型号: MC74LVX00M
厂商: ON Semiconductor
文件页数: 4/7页
文件大小: 0K
描述: IC GATE NAND QUAD 2INP 14-SOEIAJ
标准包装: 50
系列: 74LVX
逻辑类型: 与非门
电路数: 4
输入数: 2
电源电压: 2 V ~ 3.6 V
电流 - 静态(最大值): 2µA
输出电流高,低: 4mA,4mA
逻辑电平 - 低: 0.5 V ~ 0.8 V
逻辑电平 - 高: 1.5 V ~ 2.4 V
额定电压和最大 CL 时的最大传播延迟: 9.7ns @ 3V ~ 3.6V,50pF
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
供应商设备封装: SOEIAJ-14
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
包装: 管件
MC74LVX00
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
Parameter
Test Conditions
TA = 25°C
TA = 40 to 85°C
Unit
Min
Typ
Max
Min
Max
tPLH,
tPHL
Propagation Delay, Input to
Output
VCC = 2.7 V
CL = 15 pF
CL = 50 pF
5.4
7.9
10.1
13.6
1.0
12.5
16.0
ns
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
4.1
6.6
6.2
9.7
1.0
1.0
7.5
11.0
tOSHL
tOSLH
OutputtoOutput Skew
(Note 1)
VCC = 2.7 V
CL = 50 pF
VCC = 3.3 ±0.3 V
CL = 50 pF
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGHtoLOW (tOSHL) or LOWtoHIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
TA = 25°C
TA = 40 to 85°C
Unit
Min
Typ
Max
Min
Max
Cin
Input Capacitance
4
10
10
pF
CPD
Power Dissipation Capacitance (Note 2)
19
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/4 (per gate). CPD is used to determine the
noload dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 3.3 V, Measured in SOIC Package)
Symbol
Characteristic
TA = 25°C
Unit
Typ
Max
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.5
V
VOLV
Quiet Output Minimum Dynamic VOL
0.3
0.5
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
Figure 3. Switching Waveforms
VCC
GND
50%
50% VCC
A or B
O
tPHL
tPLH
*Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
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