参数资料
型号: MC74VHCT50AMG
厂商: ON Semiconductor
文件页数: 1/6页
文件大小: 0K
描述: IC BUFF/LVL SHFTR N-INV 14SOEIAJ
产品变化通告: Product Discontinuation 30/Sept/2011
标准包装: 50
系列: 74VHCT
逻辑类型: 缓冲器/线路驱动器,非反相
元件数: 6
每个元件的位元数: 1
输出电流高,低: 8mA,8mA
电源电压: 2 V ~ 5.5 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
供应商设备封装: SOEIAJ-14
包装: 管件
Semiconductor Components Industries, LLC, 2014
March, 2014 Rev. 9
1
Publication Order Number:
MC74VHCT50A/D
MC74VHCT50A
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTLCompatible Inputs
The MC74VHCT50A is a hex noninverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The device input is compatible with TTLtype input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logiclevel translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the highvoltage power supply.
The MC74VHCT50A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2.0 V
CMOSCompatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
LOGIC DIAGRAM
Y1
A1
A2
A3
A4
A5
A6
Y2
Y3
Y4
Y5
Y6
1
3
5
9
11
13
2
4
6
8
10
12
Y = A
A1
Y1
1
A2
Y2
1
A3
Y3
1
A4
Y4
1
A5
Y5
1
A6
Y6
1
LOGIC SYMBOL
14LEAD SOIC
D SUFFIX
CASE 751A
14LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
13
14
12
11
10
9
8
2
1
34567
VCC
A6
Y6
A5
Y5
A4
Y4
A1
Y1
A2
Y2
A3
Y3
GND
FUNCTION TABLE
L
H
A Input
Y Output
L
H
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
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