
16
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
H13
VDDIODDR
DDR_IO
DDR_D2
I/O
—
HiZ
G17
VDDIODDR
DDR_IO
DDR_D3
I/O
—
HiZ
G16
VDDIODDR
DDR_IO
DDR_D4
I/O
—
HiZ
H15
VDDIODDR
DDR_IO
DDR_D5
I/O
—
HiZ
F17
VDDIODDR
DDR_IO
DDR_D6
I/O
—
HiZ
G15
VDDIODDR
DDR_IO
DDR_D7
I/O
—
HiZ
F16
VDDIODDR
DDR_IO
DDR_D8
I/O
—
HiZ
E17
VDDIODDR
DDR_IO
DDR_D9
I/O
—
HiZ
G14
VDDIODDR
DDR_IO
DDR_D10
I/O
—
HiZ
E16
VDDIODDR
DDR_IO
DDR_D11
I/O
—
HiZ
D17
VDDIODDR
DDR_IO
DDR_D12
I/O
—
HiZ
C18
VDDIODDR
DDR_IO
DDR_D13
I/O
—
HiZ
D16
VDDIODDR
DDR_IO
DDR_D14
I/O
—
HiZ
C17
VDDIODDR
DDR_IO
DDR_D15
I/O
—
HiZ
B16
VDDIODDR
DDR_IO
DDR_D16
I/O
—
HiZ
B18
VDDIODDR
DDR_IO
DDR_D17
I/O
—
HiZ
C15
VDDIODDR
DDR_IO
DDR_D18
I/O
—
HiZ
A18
VDDIODDR
DDR_IO
DDR_D19
I/O
—
HiZ
C16
VDDIODDR
DDR_IO
DDR_D20
I/O
—
HiZ
C14
VDDIODDR
DDR_IO
DDR_D21
I/O
—
HiZ
D15
VDDIODDR
DDR_IO
DDR_D22
I/O
—
HiZ
B14
VDDIODDR
DDR_IO
DDR_D23
I/O
—
HiZ
A15
VDDIODDR
DDR_IO
DDR_D24
I/O
—
HiZ
A14
VDDIODDR
DDR_IO
DDR_D25
I/O
—
HiZ
E12
VDDIODDR
DDR_IO
DDR_D26
I/O
—
HiZ
A11
VDDIODDR
DDR_IO
DDR_D27
I/O
—
HiZ
B11
VDDIODDR
DDR_IO
DDR_D28
I/O
—
HiZ
F12
VDDIODDR
DDR_IO
DDR_D29
I/O
—
HiZ
A10
VDDIODDR
DDR_IO
DDR_D30
I/O
—
HiZ
E11
VDDIODDR
DDR_IO
DDR_D31
I/O
—
HiZ
G12
VDDIODDR
DDR_IO
DDR_DQM0
O
—
O
E15
VDDIODDR
DDR_IO
DDR_DQM1
O
—
O
B15
VDDIODDR
DDR_IO
DDR_DQM2
O
—
O
D12
VDDIODDR
DDR_IO
DDR_DQM3
O
—
O
E18
VDDIODDR
DDR_IO
DDR_DQS0
I/O
—
I, PD
G18
VDDIODDR
DDR_IO
DDR_DQS1
I/O
—
I, PD
B17
VDDIODDR
DDR_IO
DDR_DQS2
I/O
—
I, PD
B13
VDDIODDR
DDR_IO
DDR_DQS3
I/O
—
I, PD
D18
VDDIODDR
DDR_IO
DDR_DQSN0
I/O
—
I, PU
F18
VDDIODDR
DDR_IO
DDR_DQSN1
I/O
—
I, PU
A17
VDDIODDR
DDR_IO
DDR_DQSN2
I/O
—
I, PU
A13
VDDIODDR
DDR_IO
DDR_DQSN3
I/O
—
I, PU
C8
VDDIODDR
DDR_IO
DDR_CS
O
—
O
Table 4-1.
SAMA5D3 Pinout for 324-ball LFBGA Package (Continued)
Pin
Power Rail
I/O Type
Primary
Alternate
PIO Peripheral A
PIO Peripheral B
PIO Peripheral C
Reset State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD, HiZ,
ST