参数资料
型号: MC850DECVR50BUR2
厂商: Freescale Semiconductor
文件页数: 26/72页
文件大小: 0K
描述: IC MPU PQUICC 50MHZ 256-PBGA
标准包装: 500
系列: MPC8xx
处理器类型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
电压: 3.3V
安装类型: 表面贴装
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(23x23)
包装: 带卷 (TR)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
32
Freescale Semiconductor
Bus Signal Timing
Table 8 shows the PCMCIA timing for the MPC850.
Table 8. PCMCIA Timing
Num
Characteristic
50MHz
66MHz
80 MHz
FFACTOR Unit
Min
Max
Min
Max
Min
Max
P44
A[6–31], REG valid to PCMCIA strobe
asserted. 1
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAIT_B signal is detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
13.00
21.00
17.00
0.750
ns
P45
A[6–31], REG valid to ALE negation.1
18.00
28.00
23.00
1.000
ns
P46
CLKOUT to REG valid
5.00
13.00
8.00
16.00
6.00
14.00
0.250
ns
P47
CLKOUT to REG Invalid.
6.00
9.00
7.00
0.250
ns
P48
CLKOUT to CE1, CE2 asserted.
5.00
13.00
8.00
16.00
6.00
14.00
0.250
P49
CLKOUT to CE1, CE2 negated.
5.00
13.00
8.00
16.00
6.00
14.00
0.250
ns
P50
CLKOUT to PCOE, IORD, PCWE,
IOWR assert time.
11.00
11.00
11.00
ns
P51
CLKOUT to PCOE, IORD, PCWE,
IOWR negate time.
2.00
11.00
2.00
11.00
2.00
11.00
ns
P52
CLKOUT to ALE assert time
5.00
13.00
8.00
16.00
6.00
14.00
0.250
ns
P53
CLKOUT to ALE negate time
13.00
16.00
14.00
0.250
ns
P54
PCWE, IOWR negated to D[0–31]
invalid.1
3.00
6.00
4.00
0.250
ns
P55
WAIT_B valid to CLKOUT rising edge.1
8.00
8.00
8.00
ns
P56
CLKOUT rising edge to WAIT_B
invalid.1
2.00
2.00
2.00
ns
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