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参数资料
型号： MC8641DVU1333JB
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 166.66 MHz, MICROPROCESSOR, CBGA1023
封装： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件页数： 71/130页
文件大小： 1493K
代理商： MC8641DVU1333JB
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
45
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8641.
10.1
Local Bus DC Electrical Characteristics
Table 40 provides the DC electrical characteristics for the local bus interface operating at OVDD = 3.3 V
DC.
10.2
Local Bus AC Electrical Specifications
Table 41 describes the timing parameters of the local bus interface at OVDD = 3.3 V with PLL enabled.
For information about the frequency range of local bus see Section 18.1, “Clock Ranges.”
Table 40. Local Bus DC Electrical Characteristics (3.3 V DC)
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
(VIN
1 = 0 V or V
IN = OVDD)
IIN
—±5
μA
High-level output voltage
(OVDD = min, IOH = –2 mA)
VOH
OVDD – 0.2
—
V
Low-level output voltage
(OVDD = min, IOL = 2 mA)
VOL
—0.2
V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 41. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled
Parameter
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
7.5
—
ns
2
Local Bus Duty Cycle
tLBKH/tLBK
45
55
%
—
LCLK[n] skew to LCLK[m] or LSYNC_OUT
tLBKSKEW
—
150
ps
7, 8
Input setup to local bus clock (except LGTA/LUPWAIT)
tLBIVKH1
1.8
—
ns
3, 4
LGTA/LUPWAIT input setup to local bus clock
tLBIVKH2
1.7
—
ns
3, 4
Input hold from local bus clock (except LGTA/LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
LGTA/LUPWAIT input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output transition to LAD/LDP output transition (LATCH hold
time)
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—2.0
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—2.2
ns
—
Local bus clock to address valid for LAD
tLBKHOV3
—2.3
ns
—
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