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参数资料
| 型号： | MC8641DVU1500JC |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封装： | 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023 |
| 文件页数： | 12/140页 |
| 文件大小： | 1484K |
| 代理商： | MC8641DVU1500JC |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
109
Clocking
20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when
the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down
resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down
the value of the net at reset, then a pullup or active driver is needed.
21. Should be pulled down at reset if platform frequency is at 400 MHz.
22. These pins require 4.7-k
Ω pull-up or pull-down resistors and must be driven as they are used to determine PLL configuration
ratios at reset.
23. This output is actively driven during reset rather than being tri-stated during reset.
24 These JTAG pins have weak internal pull-up P-FETs that are always enabled.
25. This pin should NOT be pulled down (or driven low) during reset.
26.These are test signals for factory use only and must be pulled up (100-
Ω to 1- kΩ.) to OVDD for normal machine operation.
27. Dn_MDIC[0] should be connected to ground with an 18-
Ω resistor +/- 1-Ω and Dn_MDIC[1] should be connected Dn_GVDD
with an 18-
Ω resistor +/- 1-Ω. These pins are used for automatic calibration of the DDR IOs.
28. Pin N18 is recommended as a reference point for determining the voltage of VDD_PLAT and is hence considered as the
VDD_PLAT sensing voltage and is called SENSEVDD_PLAT.
29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLAT and is called SENSEVSS_PLAT.
30.This pin should be pulled to ground with a 200-
Ω resistor.
31.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve
tracking and regulation.
32. Must be tied low if unused
33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull up/down
option to allow flexibility of future designs.
34. Used as serial data output for SRIO 1x/4x link.
35. Used as serial data input for SRIO 1x/4x link.
36.This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively
driven.
37.This pin is only an output in FIFO mode when used as Rx Flow Control.
38.This pin functions as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION in device sleep
mode.
39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes).
40. See Section 18.4.2, “Platform to FIFO Restrictions” for clock speed limitations for this pin when used in FIFO mode.
41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The
phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.
42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
Special Notes for Single Core Device:
S1. Solder ball for this signal will not be populated in the single core package.
S2. The PLL filter from VDD_Core1 to AVDD_Core1 should be removed. AVDD_Core1 should be pulled to ground with a weak
(2–10 k
Ω) resistor. See Section 20.2.1, “PLL Power Supply Filtering” for more details.
S3. This pin should be pulled to GND for the single core device.
S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.
18 Clocking
This section describes the PLL configuration of the MPC8641. Note that the platform clock is identical to
the MPX clock.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC8641DVU1500K | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DVU1500KB | 功能描述:微处理器 - MPU G8 REV 2.0 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC8641DVU1500KC | 功能描述:微处理器 - MPU G8 REV 2.1 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC8641DVU1500KE | 功能描述:微处理器 - MPU G8 REV3 1.1V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC8641DVU1500N | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
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