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参数资料
型号： MC8641DVU1500KB
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 166.66 MHz, MICROPROCESSOR, CBGA1023
封装： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件页数： 64/130页
文件大小： 1493K
代理商： MC8641DVU1500KB
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
39
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1 a 125-MHz TBI receive clock
is supplied on TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas
for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the
TSEC_GTX_CLK125 pin in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in Table 34.
A timing diagram for TBI receive appears in Figure 18.
.
Figure 18. TBI Single-Clock Mode Receive AC Timing Diagram
8.2.6
RGMII and RTBI AC Timing Specifications
Table 35 presents the RGMII and RTBI AC timing specifications.
Table 34. TBI single-clock Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period
tTRR
1
1 ±100 ppm tolerance on RX_CLK frequency
7.5
8.0
8.5
ns
RX_CLK duty cycle
tTRRH/tTRR
40
50
60
%
RX_CLK peak-to-peak jitter
tTRRJ
——
250
ps
Rise time RX_CLK (20%–80%)
tTRRR
——
1.0
ns
Fall time RX_CLK (80%–20%)
tTRRF
——
1.0
ns
RCG[9:0] setup time to RX_CLK rising edge
tTRRDVKH
2.0
——ns
RCG[9:0] hold time to RX_CLK rising edge
tTRRDXKH
1.0
——ns
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with L/TVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
5
–500
0
500
ps
Data to clock input skew (at receiver) 2
tSKRGT
1.0
—
2.8
ns
tTRR
tTRRH
tTRRF
tTRRR
RX_CLK
RCG[9:0]
valid data
tTRRDXKH
tTRRDVKH
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