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| 型号： | MC8641DVU1500KE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166.66 MHz, MICROPROCESSOR, CBGA1023 |
| 封装： | 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023 |
| 文件页数： | 8/130页 |
| 文件大小： | 1493K |
| 代理商： | MC8641DVU1500KE |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
105
Clocking
18 Clocking
This section describes the PLL configuration of the MPC8641. Note that the platform clock is identical to
the MPX clock.
18.1
Clock Ranges
Table 64 provides the clocking specifications for the processor cores and Table 65 provides the clocking
specifications for the memory bus. Table 66 provides the clocking for the Platform/MPX bus and Table 67
provides the clocking for the Local bus.
37.This pin is only an output in FIFO mode when used as Rx Flow Control.
38.This pin functions as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION in device sleep
mode.
39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes).
40. See Section 18.4.2, “Platform to FIFO Restrictions” for clock speed limitations for this pin when used in FIFO mode.
41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps.
The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.
42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
Special Notes for Single Core Device:
S1. Solder ball for this signal will not be populated in the single core package.
S2. The PLL filter from VDD_Core1 to AVDD_Core1 should be removed. AVDD_Core1 should be pulled to ground with a weak
(2–10 k
Ω) resistor. See Section 20.2.1, “PLL Power Supply Filtering” for more details.
S3. This pin should be pulled to GND for the single core device.
S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.
Table 64. Processor Core Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1250MHz
1333MHz
1500 MHz
Min
Max
Min
Max
Min
Max
Min
Max
e600 core processor frequency
800
1000
800
1250
800
1333
800
1500
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.
Table 63. MPC8641 Signal Reference by Functional Block (continued)
Name1
Package Pin Number
Pin Type
Power Supply
Notes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC8641DVU1500N | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641HX1000G | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641HX1000GB | 功能描述:微处理器 - MPU G8 REV 2.0 1.05V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC8641HX1000GC | 功能描述:IC MPU SGL E600 CORE 994FCCBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC86xx 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| MC8641HX1000GE | 功能描述:微处理器 - MPU G8 REV 3.0 1.05V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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