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| 型号： | MC8641HX1250KB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封装： | 33 X 33 MM, CERAMIC, BGA-1023 |
| 文件页数： | 101/140页 |
| 文件大小： | 1484K |
| 代理商： | MC8641HX1250KB |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
63
High-Speed Serial Interfaces (HSSI)
The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 39. Receiver of SerDes Reference Clocks
13.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8641D SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential
peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire
of the differential pair must have a single-ended swing less than 800mV and greater than
200mV. This requirement is the same for both external DC-coupled or AC-coupled connection.
— For external DC-coupled connection, as described in section 13.2.1, the maximum average
current requirements sets the requirement for average voltage (common mode voltage) to be
between 100 mV and 400 mV. Figure 40 shows the SerDes reference clock input requirement
for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND. Each signal wire of the differential inputs is allowed to swing below and above the
command mode voltage (SGND). Figure 41 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude
(single-ended swing) must be between 400mV and 800mV peak-peak (from Vmin to Vmax)
with SDn_REF_CLK either left unconnected or tied to ground.
—The SDn_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows
the SerDes reference clock input requirement for single-ended signaling mode.
Input
Amp
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC8641HX1250N | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641HX1333G | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641HX1333H | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641HX1333J | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641HX1333JB | 功能描述:微处理器 - MPU G8 REV 2.0 1.05V 105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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