Serial Peripheral Interface (SPI) Module
MC68HC908QC16 MC68HC908QC8 MC68HC908QC4 Data Sheet, Rev. 5
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Freescale Semiconductor
15.3.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
In a multi-SPI system, configure the SPI modules as master or slave before
enabling them. Enable the master SPI before enabling the slave SPI.
Disable the slave SPI before disabling the master SPI. See
15.8.1 SPIOnly a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
Figure 15-3. Full-Duplex Master-Slave Connections
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
master also controls the shift register of the slave peripheral.
While the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the
master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same
time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal
operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and
control register (SPSCR) with SPRF set and then reading the SPI data register (SPDR). Writing to SPDR
clears SPTE.
15.3.2 Slave Mode
The SPI operates in slave mode when SPMSTR is clear. In slave mode, the SPSCK pin is the input for
the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must
In a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register,
and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data
register before another full byte enters the shift register.
SHIFT REGISTER
BAUD RATE
GENERATOR
MASTER MCU
SLAVE MCU
VDD
MOSI
MISO
SPSCK
SS