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参数资料
| 型号： | MC9328MX21CVM |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289 |
| 封装： | 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-289 |
| 文件页数： | 79/100页 |
| 文件大小： | 1979K |
| 代理商： | MC9328MX21CVM |
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MC9328MX21 Technical Data, Rev. 3.4
8
Freescale Semiconductor
Signal Descriptions
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [17:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are
multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is multiplexed with
BMI_WRITE of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT.
FLM_VSYNC
(or simply referred
to as VSYNC)
Frame Sync or Vsync—This signal also serves as the clock signal output for gate
driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with BMI_RXF_FULL
and BMI_WAIT of the BMI.
LP_HSYNC (or simply
referred to as HSYNC)
Line Pulse or HSync
LSCLK
Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI.
OE_ACD
Alternate Crystal Direction/Output Enable.
CONTRAST
This signal is used to control the LCD bias voltage as contrast control. This signal is multiplexed with the
BMI_READ from BMI.
SPL_SPR
Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
PS
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the
SLCDC1_CS.
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This
signal is multiplexed with the SLCDC1_RS.
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is
multiplexed with SLCDC1_D0.
Smart LCD Controller
SLCDC1_CLK
SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are
SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.
SLCDC1_CS
SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations.
These are PS and SD2_CMD signals of LCDC and SD2, respectively.
SLCDC1_RS
SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal
locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.
SLCDC1_D0
SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations.
These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a
parallel data interface is used.
SLCDC1_DAT[15:0] SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are
multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further
alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.
SLCDC2_CLK
SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK
signal from SSI3.
SLCDC2_CS
SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_TXD signal from SSI3.
SLCDC2_RS
SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with
SSI3_RXD signal from SSI3.
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9328MX21CVM | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21CVMR2 | 功能描述:处理器 - 专门应用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21DVG | 制造商:Rochester Electronics LLC 功能描述:DB I.MX21 - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9328MX21DVH | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:i.MX family of microprocessors |
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