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| 型号： | MC9328MX21SVM |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 88/88页 |
| 文件大小： | 0K |
| 描述： | IC MPU I.MX21S 289-MAPBGA |
| 标准包装： | 90 |
| 系列： | i.MX21 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 32-位 |
| 速度： | 266MHz |
| 连通性： | 1 线，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外围设备： | DMA，I²S，LCD，POR，PWM，WDT |
| 输入/输出数： | 192 |
| 程序存储器类型： | ROMless |
| 电压 - 电源 (Vcc/Vdd)： | 1.45 V ~ 3.3 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 289-LFBGA |
| 包装： | 托盘 |
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Signal Descriptions
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
9
PC_POE
PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is
multiplexed with NFCLE signal of NF.
PC_RW
PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read
access and negated low for write access. This signal is multiplexed with NFRE signal of NF.
PC_PWRON
PCMCIA input signal to indicate that the card power has been applied and stabilized.
CSPI
CSPI1_MOSI
Master Out/Slave In signal
CSPI1_MISO
Master In/Slave Out signal
CSPI1_SS[2:0]
Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and
CSPI1_SS1 is multiplexed with EXT_DMAGRANT.
CSPI1_SCLK
Serial Clock signal
CSPI1_RDY
Serial Data Ready signal. Also multiplexed with EXT_DMAREQ.
CSPI2_MOSI
Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG.
CSPI2_MISO
Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG.
CSPI2_SS[2:0]
Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS,
USBH2_RXDP and USBH2_RXDM signal of USB OTG
CSPI2_SCLK
Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and
Reset Controller module.
TOUT1
(or simply TOUT)
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1
and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT.
TOUT2
Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.
TOUT3
Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.
USB On-The-Go
USB_BYP
USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO.
USB_PWR
USB Power output signal
USB_OC
USB Over current input signal. This signal can only be used for USB function, not for GPIO.
USBG_RXDP
USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.
USBG_RXDM
USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.
USBG_TXDP
USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.
USBG_TXDM
USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.
USBG_RXDAT
USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USBG_OE
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
USBG_ON
USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.
USBG_FS
USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT
signal of USB OTG. This signal is muxed with SLCDC1_DAT10.
Table 2. i.MX21S Signal Descriptions (Continued)
Signal Name
Function/Notes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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