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参数资料
| 型号： | MC9328MX21SVMR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 27/88页 |
| 文件大小： | 0K |
| 描述： | IC MPU I.MX21S 289-MAPBGA |
| 标准包装： | 1,000 |
| 系列： | i.MX21 |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 32-位 |
| 速度： | 266MHz |
| 连通性： | 1 线，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外围设备： | DMA，I²S，LCD，POR，PWM，WDT |
| 输入/输出数： | 192 |
| 程序存储器类型： | ROMless |
| 电压 - 电源 (Vcc/Vdd)： | 1.45 V ~ 3.3 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 289-LFBGA |
| 包装： | 带卷 (TR) |
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Specifications
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
33
3.11.2
SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the Interrupt
Period during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
Figure 23. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps
the clock running, and allows the user to submit commands as normal. After all commands are submitted,
the user can switch back to the data transfer operation and all counter and status values are resumed as
access continues.
Figure 24. SDIO ReadWait Timing Diagram
Command read cycle
NRC
8
–
Clock cycles
Command-command cycle
NCC
8
–
Clock cycles
Command write cycle
NWR
2
–
Clock cycles
Stop transmission cycle
NST
2
Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC100) defined in CSD register bit[111:104]
Table 23. Timing Values for Figure 18 through Figure 22 (Continued)
Parameter
Symbol
Minimum
Maximum
Unit
Interrupt Period
IRQ
DAT[1]
For 4-bit
L H
Interrupt Period
DAT[1]
For 1-bit
CMD
Content
S T
E Z Z P
E Z Z
******
Z Z
Response
CRC
S
Z
E
S
Block Data
E
S
Block Data
DAT[1]
For 4-bit
DAT[2]
For 4-bit
CMD
******
P S T
E Z Z
******
CMD52
Z
CRC
E Z Z
S
Block Data
L L L L L L L L L L L L L L L L L L L L L H Z S
E
S
Block Data
E
Block Data
Z Z L H
E
S
Block Data
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9328MX21VG | 制造商:Rochester Electronics LLC 功能描述:APPLICATIONS PROCESSOR - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21VH | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21VK | 功能描述:处理器 - 专门应用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
| MC9328MX21VK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21VKR2 | 功能描述:处理器 - 专门应用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
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