参数资料
型号: MC9328MXLCVF15R2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 150 MHz, RISC PROCESSOR, PBGA225
封装: 13 X 13 MM, 0.80 MM PITCH, PLASTIC, BGA-225
文件页数: 12/84页
文件大小: 1448K
代理商: MC9328MXLCVF15R2
MC9328MXL Advance Information, Rev. 5.1
2
Freescale Semiconductor
Introduction
Figure 1. MC9328MXL Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
A signal is an electronic construct whose state conveys or changes in state convey information.
A pin is an external physical connection. The same pin can be used to connect a number of signals.
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and
high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are
hexadecimal.
Watchdog
GPIO
LCD Controller
JTAG/ICE
CGM
Timer 1 & 2
PWM
Standard
Bootstrap
Connectivity
System Control
I2C
MMC/SD
SPI 1 and
UART 1
UART 2
USB Device
Memory Stick
Human Interface
Video Port
Multimedia
Multimedia
Power
RTC
Bus
DMAC
Interrupt
VMMU
CPU Complex
MC9328MXL
I Cache
AIPI 1
AIPI 2
D Cache
EIM &
ARM9TDMI
System I/O
Control
(PLLx2)
Controller
Control
(11 Chnl)
SDRAMC
Accelerator
SPI 2
Host Controller
SSI/I2S
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