参数资料
型号: MC9328MXLDVF20
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA225
封装: 13 X 13 MM, 0.80 MM PITCH, PLASTIC, BGA-225
文件页数: 6/82页
文件大小: 1452K
代理商: MC9328MXLDVF20
14
MC9328MXL Advance Information
MOTOROLA
Specifications
3.6 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock freq range
Vcc = 1.8V
5
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
30
MHz
Double clock freq range
Vcc = 1.8V
80
220
MHz
Pre-divider factor (PD)
1
16
Total multiplication factor (MF)
Includes both integer
and fractional parts
5–
15
MF integer part
5
15
MF numerator
Should be less than the
denominator
0
1022
MF denominator
1
1023
Pre-multiplier lock-in time
312.5
sec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
250
280
(56
s)
300
Tref
Freq lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
220
250
(50
s)
270
Tref
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
300
350
(70
s)
400
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
270
320
(64
s)
370
Tref
Freq jitter (p-p)
0.005
(0.01%)
0.01
2Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
1.0
(10%)
1.5
ns
Power supply voltage
1.7
2.5
V
Power dissipation
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
––
4
mW
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