参数资料
型号: MC9328MXLVM20
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
封装: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件页数: 24/90页
文件大小: 1242K
代理商: MC9328MXLVM20
Functional Description and Application Information
MC9328MXL Technical Data, Rev. 8
30
Freescale Semiconductor
4.4.3
EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MXL, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown
in Figure 5, and Table 12 defines the parameters of signals.
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
ns
2EB assertion time
See note 2
ns
3CS5 pulse width
3T
ns
4RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5
Address inactived after CS negated
0.09
ns
6
Wait asserted after CS5 asserted
1020T
ns
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
ns
9
Data ready after CS5 is asserted
T
ns
10
CS deactive to next CS active
T
ns
11
EB negate after CS negate
0.5T
0.5T+0.5
12
Wait becomes low after CS5 asserted
0
1019T
ns
13
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MXL
Product
Family
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