- 您现在的位置：买卖IC网 > PDF目录80564 > MC9328MXLVP20R2 (MOTOROLA INC) 200 MHz, RISC PROCESSOR, PBGA225 PDF资料下载
参数资料
| 型号： | MC9328MXLVP20R2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 200 MHz, RISC PROCESSOR, PBGA225 |
| 封装： | 13 X 13 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BGA-225 |
| 文件页数： | 51/82页 |
| 文件大小： | 1452K |
| 代理商： | MC9328MXLVP20R2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页
Specifications
MOTOROLA
MC9328MXL Advance Information
55
Figure 44. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the
clock running, and allows the user to submit commands as normal. After all commands are submitted, the
user can switch back to the data transfer operation and all counter and status values are resumed as access
continues.
Figure 45. SDIO ReadWait Timing Diagram
3.12 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
Interrupt Period
IRQ
DAT[1]
For 4-bit
L H
Interrupt Period
DAT[1]
For 1-bit
CMD
Content
S T
E Z Z P
E Z Z
******
Z Z
Response
CRC
S
Z
E
S
Block Data
E
S
Block Data
DAT[1]
For 4-bit
DAT[2]
For 4-bit
CMD
******
P S T
E Z Z
******
CMD52
Z
CRC
E Z Z
S
Block Data
L L L L L L L L L L L L L L L L L L L L L H Z S
E
S
Block Data
E
Block Data
Z Z L H
E
S
Block Data
相关PDF资料 |
PDF描述 |
|---|---|
| MPC880ZP80 | 32-BIT, 80 MHz, RISC PROCESSOR, PBGA357 |
| MC9S08LG32CLF | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP48 |
| MSP430F123IRHB | 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQCC32 |
| M306V7MJ-XXXFP | 16-BIT, MROM, 16.1 MHz, MICROCONTROLLER, PQFP100 |
| MB95F134JBWPF | 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9328MXS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Advance Information |
| MC9328MXSCVF10 | 制造商:Rochester Electronics LLC 功能描述:REDUCED FEATURE I.MXL - Bulk 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
| MC9328MXSCVF10(R2) | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Advance Information |
| MC9328MXSCVF10R2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Advance Information |
| MC9328MXSCVP10 | 功能描述:处理器 - 专门应用 REDUCED FEATURE I.MXL RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432 |
发布紧急采购，3分钟左右您将得到回复。