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参数资料
型号： MC9RS08KA2CPC
厂商： Freescale Semiconductor
文件页数： 5/136页
文件大小： 0K
描述： IC MCU 8-BIT 2K FLASH 8-PDIP
产品培训模块： Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
标准包装： 50
系列： RS08
核心处理器： RS08
芯体尺寸： 8-位
速度： 10MHz
外围设备： LVD，POR，WDT
输入/输出数： 4
程序存储器容量： 2KB（2K x 8）
程序存储器类型： 闪存
RAM 容量： 63 x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 8-DIP（0.300"，7.62mm）
包装： 管件
产品目录页面： 726 (CN2011-ZH PDF)
配用： DEMO9RS08KA2-ND - DEMO BOARD FOR 9RS08KA2
Chapter 12 Development Support
MC9RS08KA2 Series Data Sheet, Rev. 4
102
Freescale Semiconductor
Figure 12-5. BDM Target-to-Host Serial Bit Timing (Logic 0)
12.3.3
SYNC and Serial Communication Timeout
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD to answer the SYNC
request pulse. If the rising edge is not detected, the target will keep waiting indefinitely, without any
timeout limit. When a rising edge on BKGD occurs after a valid SYNC request, the BDC will drive the
BKGD pin low for exactly 128 BDC cycles.
Consider now the case where the host returns BKGD to logic 1 before 128 cycles. This is interpreted as a
valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a timeout occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred as a soft-reset to the BDC.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieving after the timeout has
occurred. A soft-reset is also used to end a READ_BLOCK or WRITE_BLOCK command.
The following describes the actual bit-time requirements for a host to guarantee logic 1 or 0 bit
transmission without the target timing out or interpreting the bit as a SYNC command:
To send a logic 0, BKGD must be kept low for a minimum of 12 BDC cycles and up to 511 BDC
cycles except for the first bit of a command sequence, which will be detected as a SYNC request.
To send a logic 1, BKGD must be held low for at least four BDC cycles, be released by the eighth
cycle, and be held high until at least the sixteenth BDC cycle.
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
DRIVE AND
PERCEIVED START
OF BIT TIME
HIGH IMPEDANCE
BKGD PIN
10 CYCLES
SPEEDUP PULSE
SPEEDUP
PULSE
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
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相关代理商/技术参数
参数描述
MC9RS08KA2CSC 功能描述:8位微控制器 -MCU 2K FLASH W/ ACMP 62 RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
MC9RS08KA2CSCR 功能描述:8位微控制器 -MCU 2K FLASH W/ ACMP 62 RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
MC9RS08KA2DB 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers
MC9RS08KA2PC 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers
MC9RS08KA2SC 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers
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