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Appendix A Electrical Characteristics
MC9S08GB/GT Data Sheet, Rev. 2.3
272
Freescale Semiconductor
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
fICGOUT
fExtal (min)
flo (min)
fExtal (max)
fICGDCLKmax
(max)
MHz
Minimum DCO clock (ICGDCLK) frequency
fICGDCLKmin
8
—
MHz
Maximum DCO clock (ICGDCLK) frequency
fICGDCLKmax
—
40
MHz
Self-clock mode (ICGOUT) frequency 1
fSelf
fICGDCLKmin
fICGDCLKmax
MHz
Self-clock mode reset (ICGOUT) frequency
fSelf_reset
5.5
8
10.5
MHz
Loss of reference frequency 2
Low range
High range
fLOR
5
50
25
500
kHz
Loss of DCO frequency 3
fLOD
0.5
1.5
MHz
Crystal start-up time 4, 5
Low range
High range
t
CSTL
t
CSTH
—
430
4
—
ms
FLL lock time 4, 6
Low range
High range
tLockl
tLockh
—
2
ms
FLL frequency unlock range
nUnlock
–4*N
4*N
counts
FLL frequency lock range
nLock
–2*N
2*N
counts
ICGOUT period jitter, 4, 7 measured at fICGOUT Max
Long term jitter (averaged over 2 ms interval)
CJitter
—
0.2
% fICG
Internal oscillator deviation from trimmed frequency 8
VDD = 1.8 – 3.6 V, (constant temperature)
VDD = 3.0 V ±10%, –40° C to 85° C
ACCint
—
±0.5
±2
%
1 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
2 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked
mode if it is not in the desired range.
3 Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external
mode (if an external reference exists) if it is not in the desired range.
4 This parameter is characterized before qualication rather than 100% tested.
5 Proper PC board layout procedures must be followed to achieve specications.
6 This specication applies to the period of time required for the FLL to lock after entering FLL engaged internal or external
modes. If a crystal/resonator is being used as the reference, this specication assumes it is already running.
7 Jitter is the average deviation from the programmed frequency measured over the specied interval at maximum f
ICGOUT.
Measurements are made with the device powered by ltered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter
percentage for a given interval.
8 See Figure A-10
Table A-9. ICG Frequency Specications (continued)
(VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 85°C Ambient)
Characteristic
Symbol
Min
Typical
Max
Unit