参数资料
型号: MC9S08LL36CLK
厂商: Freescale Semiconductor
文件页数: 7/47页
文件大小: 0K
描述: IC MCU 8BIT 36KB FLASH 80LQFP
标准包装: 90
系列: S08
核心处理器: S08
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SCI,SPI
外围设备: LCD,LVD,POR,PWM,WDT
输入/输出数: 39
程序存储器容量: 36KB(36K x 8)
程序存储器类型: 闪存
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 10x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-LQFP
包装: 托盘
产品目录页面: 727 (CN2011-ZH PDF)
ESD Protection and Latch-Up Immunity
MC9S08LL64 Series MCU Data Sheet, Rev. 7
Freescale Semiconductor
11
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human
body model
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
3
Charge
device
model
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
3
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