参数资料
型号: MC9S08LL64CLK
厂商: Freescale Semiconductor
文件页数: 26/47页
文件大小: 0K
描述: MCU 8BIT CPU 64K FLASH 80LQFP
产品培训模块: MC9S08LL64/36 LCD MCU Introduction
标准包装: 90
系列: S08
核心处理器: S08
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SCI,SPI
外围设备: LCD,LVD,POR,PWM,WDT
输入/输出数: 39
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 4K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 10x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-LQFP
包装: 托盘
产品目录页面: 727 (CN2011-ZH PDF)
MC9S08LL64 Series MCU Data Sheet, Rev. 7
AC Characteristics
Freescale Semiconductor
28
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 13. Control Timing
Num
C
Rating
Symbol
Min
Typ1
1 Typical values are based on characterization data at V
DD = 3.0 V, 25 °C unless otherwise stated.
Max
Unit
1D
Bus frequency (tcyc = 1/fBus)
VDD ≤ 2.1V
VDD > 2.1V
fBus
dc
10
20
MHz
2
D
Internal low power oscillator period
tLPO
700
1300
μs
3D
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
textrst
100
ns
4
D
Reset low drive
trstdrv
34
× t
cyc
——
ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
μs
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
tILIH, tIHIL
100
1.5
× t
cyc
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5
× t
cyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 85 °C.
6 Except for LCD pins in open drain mode.
tRise, tFall
16
23
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
5
9
ns
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