
Timer/PWM (TPM) Module
MC9S08RC/RD/RE/RG
136
MOTOROLA
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
10.6.4 PWM End-of-Duty-Cycle Events
For channels that are configured for PWM operation, there are two possibilities:
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
When the channel is configured for center-aligned PWM, the timer count matches the channel value
register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start and
at the end of the active duty cycle, which are the times when the timer counter matches the channel
value register.
10.7 TPM Registers and Control Bits
The TPM includes:
An 8-bit status and control register (TPM1SC)
A 16-bit counter (TPM1CNTH:TPM1CNTL)
A 16-bit modulo register (TPM1MODH:TPM1MODL)
Each timer channel has:
An 8-bit status and control register (TPM1CnSC)
A 16-bit channel value register (TPM1CnVH:TPM1CnVL)
Refer to the direct-page register summary in the
Memory section of this data sheet for the absolute address
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Motorola-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
10.7.1 Timer Status and Control Register (TPM1SC)
TPM1SC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.