参数资料
型号: MC9S12DG256CMFU
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80
封装: QFP-80
文件页数: 109/128页
文件大小: 2174K
代理商: MC9S12DG256CMFU
MC9S12DP256B Device User Guide — V02.13
81
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
Table 6-1 Configuration of HCS12 Core
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 8 Enhanced Capture Timer (ECT) Block
Description
Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DP256B.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module.
Name
Description
MC9S12DP256B Configuration
PUCR_RESET
PUCR reset state
$90
NUM_INT
Interrupt Request Bus Width
56
INITEE_RST
INITEE reset state
$01
INITEE_WOK
INITEE Write anytime in normal mode
INITEE register is writeable once in
normal modes
PPAGE_SMOD_ONLY
PPAGE Write only in special mode
PPAGE register is writable in all
modes,reset state of the PPAGE register is
$00
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