
Chapter 16 S12X Debug (S12XDBGV3) Module
MC9S12XF - Family Reference Manual Rev.1.17
Freescale Semiconductor
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transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a
channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This
is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state
sequencer enters state0 and the debug module is disarmed.
An XGATE S/W breakpoint request, if enabled causes a transition to the State0 and generates a breakpoint
request to the CPU12X immediately
16.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace position control
as dened by the TALIGN eld (see
Section 16.3.2.3”). If TSOURCE in the trace control register
DBGTCR are cleared then the trace buffer is disabled and the transition to Final State can only generate a
breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM
bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled, a
breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled
then when the nal state is reached it returns automatically to state0 and the debug module is disarmed.
16.4.5
Trace Buffer Operation
The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace
information in the RAM array in a circular buffer format. The RAM array can be accessed through a
register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace
buffer line is read, an internal pointer into the RAM is incremented so that the next read will receive fresh
information. Data is stored in the format shown in
Table 16-43. After each store the counter register bits
DBGCNT[6:0] are incremented. Tracing of CPU12X activity is disabled when the BDM is active but
tracing of XGATE activity is still possible. Reading the trace buffer whilst the DBG is armed returns
invalid data and the trace buffer pointer is not incremented.
16.4.5.1
Trace Trigger Alignment
Using the TALIGN bits (see
Section 16.3.2.3”) it is possible to align the trigger with the end, the middle,
or the beginning of a tracing session.
If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered.
The transition to Final State if End is selected signals the end of the tracing session. The transition to Final
State if Mid is selected signals that another 32 lines will be traced before ending the tracing session.
Tracing with Begin-Trigger starts at the opcode of the trigger.
16.4.5.1.1
Storing with Begin-Trigger
Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the
trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace
Buffer. If the trigger is at the address of the change-of-ow instruction the change of ow associated with
the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged
instruction is about to be executed then the trace is started. Upon completion of the tracing session the
breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.