- 您现在的位置：买卖IC网 > PDF目录80476 > MCAQE16G6MPP-MXA FLASH MEMORY DRIVE CONTROLLER, PQFP PDF资料下载
参数资料
| 型号： | MCAQE16G6MPP-MXA |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PQFP |
| 封装： | LQFP |
| 文件页数： | 9/65页 |
| 文件大小： | 799K |
| 代理商： | MCAQE16G6MPP-MXA |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页
NAND Flash-based Solid State Disk
17
Sep. 27. 2006
Figure 1 defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or
4 shall power-up in a PIO mode 0,1, or 2.
For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 1
defines the minimum value that shall be placed in word 68.
Both hosts and devices shall support IORDY when PIO mode 3 or 4 are the currently selected mode of operation.
DIOR-/DIOW-
WRITE DD(7:0)
READ DD(7:0)
IORDY
t1
ADDR valid
t2
(See note 1)
(See note 2)
(See note 3,3-2)
IORDY
(See note 3,3-1)
IORDY
(See note 3,3-3)
t9
t0
t3
t4
t5
t6
t6Z
tA
tC
tRD
tB
tC
NOTE:
1. Device address consists of signals CS0-, CS1- and DA(2:0)
2. Data consists of DD(7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made
by the host after tA from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases:
3-1. Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2. Device negates IORDY before tA, but causes IORDY to be asserted before tA.
IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.
3-3. Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated.
The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on
DD(7:0) for tRD before asserting IORDY.
4. DMACK- shall remain negated during a register transfer.
Figure 1. Register transfer to/from device.
t2i
4.5.1 Register Transfers
4.5 AC Characteristics
相关PDF资料 |
PDF描述 |
|---|---|
| MSP430F2416TPM | 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64 |
| MPC8545PXANGA | 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783 |
| MAX7391ASTP | 8 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MC9S12C96MPBE25 | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP52 |
| MPC8545HXATGA | 32-BIT, 1200 MHz, MICROPROCESSOR, CBGA783 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MCAQE32G5APP-0XA00 | 制造商:Samsung Semiconductor 功能描述: |
| MCAQE32G8APP-0XA00 | 制造商:Samsung SDI 功能描述:Flash Card 32G-byte 3.3V/5V Flash Disk 44-Pin Tray |
| MCAS015.XP | 制造商:Littelfuse 功能描述:FUSE - MCASE 32V 15A 1-PC CARD 制造商:Littelfuse 功能描述:RETAIL / FUSE - MCASE 32V 15A 1-pc Card |
| MCAS020.XP | 制造商:Littelfuse 功能描述:FUSE - MCASE 32V 20A 1-PC CARD 制造商:Littelfuse 功能描述:RETAIL / FUSE - MCASE 32V 20A 1-pc Card |
| MCAS025.XP | 制造商:Littelfuse 功能描述:FUSE - MCASE 32V 25A 1-PC CARD 制造商:Littelfuse 功能描述:RETAIL / FUSE - MCASE 32V 25A 1-pc Card |
发布紧急采购，3分钟左右您将得到回复。