参数资料
型号: MCF51QE96CLK
厂商: Freescale Semiconductor
文件页数: 15/38页
文件大小: 0K
描述: IC MCU 32BIT 96K FLASH 80-LQFP
产品培训模块: Flexis QE Series Low Power Features
标准包装: 90
系列: MCF51QE
核心处理器: Coldfire V1
芯体尺寸: 32-位
速度: 50MHz
连通性: I²C,SCI,SPI
外围设备: LVD,PWM,WDT
输入/输出数: 70
程序存储器容量: 96KB(96K x 8)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 24x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-LQFP
包装: 托盘
MCF51QE128 Series Data Sheet, Rev. 7
Electrical Characteristics
Freescale Semiconductor
22
Figure 14. Reset Timing
Figure 15. IRQ/KBIPx Timing
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
8
31
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
7
24
ns
10
Voltage regulator recovery time
tVRR
—4
μs
1 Typical values are based on characterization data at V
DD = 3.0V, 25°C unless otherwise stated.
2 This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt
request until it is explicitly negated by the interrupt service routine.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
Table 13. Control Timing (continued)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
textrst
RESET PIN
tIHIL
KBIPx
tILIH
IRQ/KBIPx
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