
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
MOTOROLA
USERS MANUAL
vii
8.3.1.3.1
8-, 16-, and 32-Bit Port Sizing ....................................................8-7
8.3.1.3.2
Termination ................................................................................8-7
8.3.1.3.3
Bursting Control ..........................................................................8-7
8.3.1.3.4
Address Setup and Hold Control ................................................8-8
8.3.2
Global Chip Select Operation .....................................................8-8
8.3.3
General Chip Select Operation ..................................................8-8
8.3.3.1
NonBurst Transfer with No Address Setup and Hold .....8-9
8.3.3.2
NonBurst Transfer with Address Setup ........................8-10
8.3.3.3
NonBurst Transfer With Address Setup and Hold ........8-12
8.3.3.4
Burst Transfer ...............................................................8-14
8.3.3.5
Burst Transfer With Address Setup ..............................8-16
8.3.3.6
Burst Transfer With Address Setup and Hold ...............8-18
8.3.4
Alternate Master Chip Select Operation ...................................8-21
8.3.4.1
Alternate Master NonBurst Transfer .............................8-21
8.3.4.2
Alternate Master Burst Transfer ....................................8-23
8.3.4.3
Alternate Master Burst Transfer With Address Setup and Hold
.......................................................................................8-25
8.4
Programming Model ...........................................................................8-27
8.4.1
Chip Select Registers Memory Map......................................... 8-27
8.4.2
Chip Select Controller Registers ..............................................8-29
8.4.2.1
Chip Select Address Register (CSAR0 - CSAR7) ........8-29
8.4.2.2
Chip Select Mask Register (CSMR0 - CSMR7)............ 8-30
8.4.2.3
Chip Select Control Register (CSCR0 - CSCR7) .........8-32
8.4.2.4
Default MemoryControl Register (DMCR) ....................8-38
Section 9
Parallel Port (General-Purpose I/O) Module
9.1
Introduction ...........................................................................................9-1
9.2
Parallel Port Operation .........................................................................9-1
9.3
Programming Model .............................................................................9-1
9.3.1
Parallel Port Registers Memory Map ..........................................9-1
9.3.2
Parallel Port Registers ................................................................9-2
9.3.2.1
Port A Data Direction Register (PADDR) ........................9-2
9.3.2.2
Port A Data Register (PADAT) .......................................9-2
Section 10
DRAM Controller
10.1
Introduction .........................................................................................10-1
10.1.1
Features ...................................................................................10-1
10.2
DRAM Controller I/O ..........................................................................10-1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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