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参数资料
| 型号： | MCF5206EFT54 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT COLDF 54MHZ 160-QFP |
| 标准包装： | 24 |
| 系列： | MCF520x |
| 核心处理器： | Coldfire V2 |
| 芯体尺寸： | 32-位 |
| 速度： | 54MHz |
| 连通性： | EBI/EMI，I²C，UART/USART |
| 外围设备： | DMA，WDT |
| 输入/输出数： | 8 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 160-BQFP |
| 包装： | 托盘 |
| 配用： | M5206EC3-ND - KIT EVAL FOR MCF5206E W/ETHERNET |
MOTOROLA
MCF5206e Integrated ColdFire Microprocessor Product Brief
7
MCF5206e Overview
1.1.11.4 Interrupt Controller
The interrupt controller provides user-programmable control of 3 or 7 external interrupt to any one of 7
interrupt levels and 4 priority levels. The 3 external interrupt signals can be congured as either xed
interrupt levels 1, 4, and 7, or as a 7-level encoded interrupt. The external interrupts can also be programmed
to any one of the four priority levels within the respective interrupt levels.
1.1.11.5 System Protection
The MCF5206e processor contains a 16-bit software watchdog timer with an 8-bit prescaler. The
programmable software watchdog timer provides either a level 7 interrupt or a hardware reset on timeout.
The MCF5206e processor also contains a reset status register that indicates the cause of the last reset.
1.1.11.6 JTAG
To help with system diagnostics and testing during manufacture, the MCF5206e processor includes
dedicated user-accessible test logic that complies with the IEEE 1149.1 standard for boundary scan
testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE
1149.1 standard.
1.1.12 System Debug Interface
The ColdFire interface supports real-time trace and background debug mode. A 4-pin background debug
mode (BDM) interface provides system debug. The BDM is a superset of the BDM interface provided on
Motorola’s 683xxx family of parts.
In real-time trace, 4 status lines provide information on processor activity in real time (PST pins). A 4-bit
wide debug data bus (DDATA) displays operand data, which helps track the machine’s dynamic execution
path as the change-of-ow instructions execute. These signals are multiplexed with the 8-bit parallel port
for application development which does not use real-time trace.
1.1.13 System Diagrams
This section includes system and pinout diagrams. Figure 2 shows the system of the MCF5206e device.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MCF5206EPB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire Version 2 core, 32-bit data base |
| MCF5206EPB/D | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MCF5206e Integrated ColdFire Microprocessor Product Brief |
| MCF5206EPD | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire Version 2 core, 32-bit data base |
| MCF5206EUD | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire Version 2 core, 32-bit data base |
| MCF5206EUM | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:ColdFire Version 2 core, 32-bit data base |
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