参数资料
型号: MCF5207CVM166
厂商: Freescale Semiconductor
文件页数: 14/46页
文件大小: 0K
描述: IC MCU 32BIT RISC 144-MAPBGA
标准包装: 160
系列: MCF520x
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 166.67MHz
连通性: EBI/EMI,I²C,SPI,UART/USART
外围设备: DMA,WDT
输入/输出数: 30
程序存储器类型: ROMless
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LBGA
包装: 托盘
Electrical Characteristics
MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
21
5.4.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins.
The filter shown in Figure 11 should be connected between the board VDD and the PLLVDD pins. The
resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible.
Figure 11. System PLL VDD Power Filter
5.4.2
Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences.
SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD.
5.4.2.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output
drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after
EVDD/SDVDD powers up before IVDD must power up. IVDD should not lead the EVDD, SDVDD, or
PLLVDD by more than 0.4 V during power ramp-up or there will be high current in the internal ESD
protection diodes. The rise times on the power supplies should be slower than 500 us to avoid turning on
the internal ESD protection clamp diodes.
5.4.2.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, sense circuits in the I/O pads cause all output drivers to be in a
high impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD
or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than
Weak Internal Pull Up Device Current, tested at VIL Max.
1
IAPU
-10
- 130
μA
Input Capacitance 2
All input-only pins
All input/output (three-state) pins
Cin
7
pF
NOTES:
1
Refer to the signals section for pins having weak internal pull-up devices.
2
This parameter is characterized before qualification rather than 100% tested.
Table 7. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Board VDD
10
Ω
0.1 F
PLL VDD Pin
10 F
GND
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