参数资料
型号: MCF52110CAE80
厂商: Freescale Semiconductor
文件页数: 3/56页
文件大小: 0K
描述: IC MCU 128K FLASH 80MHZ 64LQFP
标准包装: 160
系列: MCF521xx
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 80MHz
连通性: I²C,SPI,UART/USART
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 43
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 64-LQFP
包装: 托盘
配用: M5211DEMO-ND - KIT DEMO FOR MCF5211
MCF52110 ColdFire Microcontroller, Rev. 1
Family Configurations
Freescale Semiconductor
11
1.2.14
Real-Time Clock (RTC)
The Real-Time Clock (RTC) module maintains the system (time-of-day) clock and provides stopwatch, alarm, and interrupt
functions. It includes full clock features: seconds, minutes, hours, days and supports a host of time-of-day interrupt functions
along with an alarm interrupt.
1.2.15
Pulse-Width Modulation (PWM) Timers
The device has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated
counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to
100%. The timer supports PCM mode, which results in superior signal quality when compared to that of a conventional PWM.
The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For
higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to
form a single 16-bit channel. The module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.
1.2.16
Software Watchdog Timer
The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running
down-counter that generates a reset on underflow. The reset only happens if the SWT is enabled, and it does not reset the whole
chip. To prevent a reset, software must periodically restart the countdown.
1.2.17
Backup Watchdog Timer
The backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer, facilitates recovery from
runaway code. This timer is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown. The backup watchdog timer can be clocked by either the relaxation oscillator or the system
clock.
1.2.18
Phase-Locked Loop (PLL)
The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced
frequency divider (RFD), low-power divider status/control registers, and control logic. To improve noise immunity, the PLL,
crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
1.2.19
Interrupt Controller (INTC)
The device has a single interrupt controller that supports up to 63 interrupt sources. There are 56 programmable sources, 49 of
which are assigned to unique peripheral interrupt requests. The remaining seven sources are unassigned and may be used for
software interrupt requests.
1.2.20
DMA Controller
The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor
intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered
by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events. The DMA also
supports channel-linking capabilities.
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