参数资料
型号: MCF52233CAL60
厂商: Freescale Semiconductor
文件页数: 14/55页
文件大小: 0K
描述: IC MCU 256K FLASH 60MHZ 112-LQFP
标准包装: 60
系列: MCF5223x
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 60MHz
连通性: 以太网,I²C,SPI,UART/USART
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 73
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 112-LQFP
包装: 托盘
配用: M52233DEMO-ND - BOARD DEMO FOR MCF52233
MCF5223
5
ColdFire
Mic
roc
ontr
oller,
Re
v
.
1
0
F
reescale
Sem
ic
o
nductor
21
UART 13
UCTS1
SYNCA
URXD2
PUB[3]
PDSR[15]
J3
24
16
URTS1
SYNCB
UTXD2
PUB[2]
PDSR[14]
H3
23
15
URXD1
FEC_TXD[0]
PUB[1]
PDSR[13]
PWOR[2]
K3
32
23
UTXD1
FEC_COL
PUB[0]
PDSR[12]
PWOR[3]
L3
33
24
UART 2
UCTS2
PUC[3]
PDSR[27]
L10
61
URTS2
PUC[2]
PDSR[26]
K10
60
URXD2
PUC[1]
PDSR[25]
K11
62
UTXD2
PUC[0]
PDSR[24]
L11
63
FlexCAN
SYNCA
CANTX4
FEC_MDIO
PAS[3]
PDSR[39]
28
20
SYNCB
CANRX4
FEC_MDC
PAS[2]
PDSR[39]
27
19
VDD5,11
VDD
N/A
D7, E8
65,102
45,74
VDDX
N/A
D5, D6, E6, G5,
G6, G7, H6
14, 43
10, 31
VSS
N/A
E4, E5, E7,F4,
F5, F6, F7, F8
64,101
44,73
VSSX
N/A
15, 42
11, 30
1 The PDSR and PSSR registers are described in Chapter 14, “General Purpose I/O Module. All programmable signals default to 2mA drive in normal
(single-chip) mode.
2 All signals have a pull-up in GPIO mode.
3 The use of an external PHY limits ADC, interrupt, and QSPI functionality. It also disables the UART0/1 and timer pins.
4 The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.
5 The VDD1, VDD2, VDDPLL, and PHY_VDD pins are for decoupling only and should not have power directly applied to them.
6 For primary and GPIO functions only.
7 Only when JTAG mode is enabled.
8 For secondary and GPIO functions only.
9 RSTI has an internal pull-up resistor; however, the use of an external resistor is strongly recommended.
10 For GPIO function. Primary Function has pull-up control within the GPT module.
11 This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the Ethernet PHY.
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin Group
Primary
Function
SecondaryF
unction
Tertiary
Function
Quaternary
Function
Drive
Strength/
Control1
Wired OR
Control
Pull-up/
Pull-down2
Pin on 121
MAPBGA
Pin on 112
LQFP
Pin on 80
LQFP
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